1. Field of the Invention
The present invention generally relates to a three-dimensional (3-D) chip integration process and structure, and, more specifically, relates to a method for optimizing the yield of a three-dimensional chip integration process and 3-D chips upon completion of the integration process.
2. Description of the Related Art
This invention relates to 3-D semiconductor devices built with potentially different technologies fabricated on separate wafers, diced, and then connected together by mounting one of the dies on the other. These devices, referred to as 3-D integrated circuits (ICs), have the potential for enabling circuit performance enhancements required to meet the aggressive performance targets of future technology. These circuits contain multiple layers of active devices with vertical interconnections between the layers. In a 3-D IC, each transistor can theoretically access a greater number of nearest neighbors than a conventional two-dimensional (2-D) circuit, such that each transistor or functional block will have a higher bandwidth and thus, in the aggregate, can operate properly at higher clock cycle rates.
Three-dimensional electronics offer significant performance benefits over 2-D ICs based on the electrical and mechanical properties arising from the new geometrical arrangement provided thereby in comparison with single, planar (2-D) chips. The advantages of very high integration density on a single chip in regard to circuit performance and manufacturing economy have been recognized for some years. Increased chip functionality can be obtained at a lower manufacturing cost by forming more devices (e.g. transistors, storage cells and the like) on a single wafer. For these reasons, there is a trend toward producing larger chips and the packaging of many chips in the same package. However, while functionality and manufacturing economics may increase from increased integration density, there is a limit to performance gain with single chips and multi-chip packages due to signal propagation increases with increased connection length. Some of these limitations may be overcome with 3-D geometries but may also suffer limitations due to interchip connections in known chip stacking technologies. Additional projected advantages of 3-D semiconductor devices include, but are not limited to: increased packing density of chips, reduced wire delay, higher fan-out, reduced noise, lower power, and enhanced circuit functionality.
Known chip stacking technologies and their problems include 1) connection density versus yield, and 2) number of connections between chips, especially using edge bonding. A good example is the merging of DRAM and logic in certain packaging operations, which has been trending towards connecting one chip directly to the face of another chip through controlled collapse chip connection (C4) solder connections. Another example is the so-called “mother/daughter” chip structure, which has been used to provide a large number of inputs/outputs (I/Os) between two chips, although it can create limitations on the available area to make connections to the outside package.
Additionally, the rapid growth of devices such as cellular phones, digital cameras, and other mobile data terminals has placed a strong demand on downsizing and densification in consideration of both the thickness and also the area of a semiconductor device. Downsizing and densification of a semiconductor device by thinning, if performed without increasing the area of the chip, would provide many desirable effects, such as increased flexibility, allowing smaller chip packages or multiple chips in the same package, and improved chip performance due to increased heat dissipation. Thinned chips can function at higher speeds and consequently increased heat dissipation, since the insulating silicon between the device and thermal management material is reduced.
Currently, there is considerable interest in creating “system-on-a-chip” solutions for different applications. Ideally, such a computing processing system is fabricated with all the necessary IC devices on a single chip. In practice, however, it is very difficult to implement a truly high-performance system because of different fabrication processes and lower manufacturing yields for the logic and memory circuits, and different preferred technologies for respective functional sections such as processors, gate arrays, memories, distributed power regulators, connectors and the like. For example, integrating functions onto a single chip generally require compromise of the performance of the logic and the performance/density of the memory. Further, the chips often become very large, and the yield of fully functional chips decreases. The use of three-dimensional integrated circuitry allows for the logic and memory to be built separately, with processes optimized for each, and then combined into a single chip stack. If the memory and logic chips are built separately, with smaller die sizes, the yields can, in theory, be greatly enhanced. Then, the separate, smaller chips can be integrated into a single module, or chip stack. Such a chip could include, for example, logic functions, and dynamic random access memory (DRAM) functions.
One problem associated with the background art, however, involves the general trend of device yield decreasing as device complexity, integration density, or chip size, increases. It has been observed that as chip area increases, the effective chip yields are reduced at nearly a linear rate. This trend can be attributed to the fact that for the same quality of semiconductor, any defect existing in a larger chip results in an overall greater area waste than is the case with smaller chip wafers. Similarly, any finite likelihood of a defect in a given element (e.g., transistor, connection, or the like), however slight, is greatly multiplied in high integration density chips and may become quite significant with increased chip area. Thus as chip size increases, the cost of manufacturing due to yield degradation becomes excessive.
One background art method of forming stacked semiconductor packages involves dipping leads of separate yet stacked chips into a soldering solution. The major disadvantage of this method is the difficulty in controlling the amount of soldering solution that contacts the stacked chips. Additionally, densely packed leads often results in short-circuiting. Another background art method involves applying a tape-automated bonding process. Bonding tape is attached to the sides of paired semiconductor chips in such a way that conductive interconnections formed on one side of the bonding tape connect the corresponding chip pads of adjacent pairs of chips. The die and circuitry on the leadframe, except for outer portions of the leadframe, are encapsulated in a mold forming a single package body for the entire semiconductor package. The disadvantage to this approach is that any need for repair of the module after package fabrication would cause the entire module to be rejected.
Semiconductor chips are typically fabricated on a single substrate such as a wafer or a panel, using wafer-level fabrication processes. One step that is often performed at the wafer level is the fabrication of contacts on the components. For example, solder bumps can be fabricated on a chip using a deposition process, permitting controlled collapse chip connections (C4) to be made for packaging. In another example, solder balls can be fabricated on semiconductor packages by bonding pre-formed balls using solder reflow performed with a furnace or a laser. Often the solder balls are arranged in a ball grid array (BGA), or a fine ball grid array (FBGA), and function as the terminal contacts for the packages. One shortcoming of these conventional contact fabrication processes is that time and materials are wasted in forming the contacts on defective and substandard components. Additionally, pressure joining processes tend to crush or compress C4s, resulting in shorting of C4 interconnects. Thus, because of the height of these connections relative to the chip, and the ease at which these connections can be damaged, another limitation is that pressure and mechanical strain must be limited while integrating chips containing these types of connections. Also, C4s will melt at high temperatures, which restrains subsequent processing conditions and operating conditions.
Further, current art teaches the thinning of chips in order to decrease the aspect ratio of vias drilled into the chip. When a via is drilled through a majority of the wafer thickness of a chip, the aspect ratio is very large, often 100:1 or more, particularly at known and foreseeable minimum feature sizes, making it difficult to fill the via with a seed metal and subsequently deposited metal to reliably and repeatably provide vertical connection between stacked up interconnect metal lines. Thinning the chip decreases the aspect ratio of the via, thereby reducing the difficulty of filling the via. However, thinned chips lack structural integrity and become difficult to handle for further processing. The prior art teaches the use of a second wafer known as a handle wafer. Under the prior art, a device wafer can be thinned by first attaching a handle wafer to one side of the device wafer, then shaving, etching, polishing, or grinding the opposite side of the device wafer. The thinned wafer is then aligned with a second wafer of normal thickness and complimentary pre-diced chips are bonded together to form a 3-D structure. Under the current art, the handle wafer is removed before dicing the 3-D structure. This implies that all chips of one wafer are bonded to corresponding chips on another wafer regardless of defects in individual chips on either wafer.
In this regard, an additional drawback experienced in the background art of forming stacked chips is the possibility of bonding a good chip site of one wafer to a bad chip site on another wafer. Bonding a defective chip to a good chip, at best, causes waste of the good chip. Such bonding may further compromise the yield because a thinned chip cannot generally be released from a chip to which it is bonded without sustaining irreparable damage. The process of forming effective chip stacks yields functional devices only if both sites are working correctly, and there is currently no method to increase the frequency of bonding good chip sites to good chip sites, thereby increasing the yield of good, functional chip stacks. Further, current methods of testing semiconductor devices for functional chips require subjecting each chip to the testing method, resulting in increased fabrication cost and time.